This invention relates generally to computer aided engineering programs and specifically to a method and apparatus for assigning and analyzing timing specifications in a computer aided engineering program.
Much of the process of creating, testing and implementing an electronic circuit has been automated by the use of computers as a design tool. The computer executes a design or engineering program that provides a human user with tools such as "capturing" a design into electronic form, editing the design with the computer, detecting errors in the design, simulating the operation of the design and translating the design into a component layout or integrated circuit mask pattern depending on the final implementation. The availability of efficient, user-friendly software tools to aid the designer has become very important as the size and complexity of circuits designs increases.
One function provided by computer aided design tools is automatic synthesis and optimization of a circuit design from a schematic diagram. The computer aided design (CAD) system is given a set of constraints, such as timing specifications, and produces a circuit that performs the logic of the schematic diagram while meeting the specified constraints. A typical constraint is, e.g., minimum propagation delay from an input to an output. The CAD system may have to improve the speed of portions of the design by implementing logic functions in combinatorial logic as opposed to standard cells, by using faster logic families or by reducing the number of components used to achieve time critical logic functions.
The synthesis and optimization of a design from a schematic diagram can be complex and time consuming both to the human designer and to the computer's resources where the circuit of the schematic diagram is large and the constraints are many and stringent. Further, requiring the designer to specify constraints to the computer program in the first place can be very burdensome and time consuming. The designer must evaluate many factors including signal relationships, manufacturing costs, the timing of external signals that the circuit must interface with, tolerances of components used in the circuit, etc.
Methods used in the past allow a designer to place constraints on the optimization and synthesis of logic from a schematic diagram by using a "delay matrix." The delay matrix approach consists of entering an N by N array of numbers specifying the minimum required delay from any input to any output in the circuit being designed. This has the disadvantage of requiring a large number of entries (up to N.sup.2) by the designer, or user, of the system. It is often difficult or impossible for the designer to annotate this information on an element by element basis in the source schematic even when the schematic is an electronic copy since so many numbers are required by each element. By only allowing constraints for the input and outputs, the traditional method tries to define the timing requirements of a circuit in a very limited way by specifying a single arrival time for every input and the minimum time for each output to become stable. Also, this does not take into account ambiguities that arise when synchronous logic elements, such as flip flops, are used in the circuit design.